Currently, there exists a trend for a flat-panel display device, such as a liquid crystal display (LCD) device and an organic light-emitting diode (OLED) display device, to be of a large size and a high resolution. For a thin film transistor (TFT) which serves as a critical control member in a flat-panel display industry, its performance becomes more and more important. An oxide TFT has carrier mobility up to 10 cm2/Vs, about 10 times the carrier mobility of an a-Si TFT. Moreover, the oxide TFT may be manufactured by sputtering, and merely a material capable of changing its target is required to be introduced, without any need to change an existing production line.
Generally, a bottom-gate oxide TFT may be manufactured by the following method.
Referring to FIG. 1, which is a flow chart of a method for manufacturing a bottom-gate TFT of an OLED array substrate in the related art, each pixel unit of the OLED array substrate includes two TFTs, i.e., a switching TFT and a driving TFT. A drain electrode of the switching TFT is required to be electrically connected to a gate electrode of the driving TFT. As shown in FIG. 1, the method for manufacturing the bottom-gate TFT of the OLED array substrate includes seven patterning processes, i.e., seven masks are used. For example, the method includes the following Steps S11 to S17.
Step S11: forming a gate electrode 102 of the switching TFT and a gate electrode 102′ of the driving TFT on a base substrate 101, and depositing a gate insulating layer (GI) 103 on the gate electrode 102 and the gate electrode 102′. A procedure of forming the gate electrode 102 and the gate electrode 102′ includes forming a gate electrode layer film, and then forming a pattern including the gate electrode 102 and the gate electrode 102′ by a single patterning process (1Mask).
Step S12: forming an active layer 104 on the gate insulating layer 103. The active layer may be made of IGZO. A procedure of forming the active layer 104 includes forming an active layer film and then forming a pattern including the active layer by a single patterning process (2Mask).
Step S13: forming an etch stop layer (ESL) 105 on the active layer 104. A procedure of forming the ESL 105 includes forming an ESL film and then forming a pattern including the ESL 105 by a single patterning process (3Mask).
Step S14: forming an aperture on the gate insulating layer 103 above the gate electrode of the driving TFT so as to connect the gate electrode 102′ of the driving TFT and a subsequently-formed drain electrode of the switching TFT. A procedure of forming the aperture includes forming a gate insulating layer pattern including the aperture by a single patterning process (4Mask).
Step S15: forming a source electrode 1061 and a drain electrode 1062 on the resultant base substrate. A procedure of forming the source electrode 1061 and the drain electrode 1062 includes forming a source/drain layer film, and then forming a pattern including the source electrode 1061 and the drain electrode 1062 by a single patterning process (5Mask).
Step S16: depositing a protective layer (PVX) 107, and forming an aperture on the protective layer 107 above the drain electrode 1062 of the switching TFT and the gate electrode of the driving TFT so as to connect the gate electrode 102′ of the driving TFT and the drain electrode 1062 of the switching TFT. A procedure of forming the aperture includes forming a protective layer pattern including the aperture by a single patterning process (6Mask).
Step S17: forming a conductive pattern 108 on the protective layer 107. The conductive pattern may be made of ITO. A procedure of forming the conductive pattern 108 includes forming a transparent conductive film, and then forming a pattern including the conductive pattern 108 by a single patterning process (7Mask).
Referring to FIG. 2, which is another flow chart showing a method for manufacturing a bottom-gate TFT of an OLED array substrate in the related art, the method includes six patterning processes, i.e., six masks are used. For example, the method includes the following steps S21 to S26.
Step S21: forming a gate electrode 202 of the switching TFT and a gate electrode 202′ of the driving TFT on a base substrate 201, and depositing a gate insulating layer (GI) 203 on the gate electrode 202 and the gate electrode 202′. A procedure of forming the gate electrode 202 and the gate electrode 202′ includes forming a gate electrode layer film, and then forming a pattern including the gate electrode 202 and the gate electrode 202′ by a single patterning process (1Mask).
Step S22: forming an active layer 204 on the gate insulating layer 203. A procedure of forming the active layer 204 includes forming an active layer film, and then forming a pattern including the active layer by a single patterning process (2Mask).
Step S23: forming an etch stop layer 205 on the active layer 204. A procedure of forming the etch stop layer 205 includes forming an etch stop layer film, and then forming a pattern including the etch stop layer 205 by a single patterning process (3Mask).
Step S24: forming a source electrode 2061 and a drain electrode 2062. A procedure of forming the source electrode 2061 and the drain electrode 2062 includes forming a source/drain layer film, and then forming a pattern including the source electrode 2061 and the drain electrode 2062 by a single patterning process (4Mask).
Step S25: forming a protective layer 207, etching a via-hole in the protective layer 207, etching off the gate insulating layer 203 on the gate electrode 202′ of the driving TFT, on the premise of preventing a metal of the drain electrode 2062 of the switching TFT from being etched, by means of different etching rates for different metals in an atmosphere used by dry etching, and forming an aperture for connecting the gate electrode 202′ of the driving TFT and the drain electrode 2062 of the switching TFT.
Step S26: forming a conductive pattern 208 on the protective layer 207. A procedure of forming the conductive pattern 208 includes forming a transparent conductive film, and then forming a pattern including the conductive pattern 208 by a single patterning process (6Mask).
In the above-mentioned two methods, six or seven patterning processes are required to be performed so as to manufacture the TFT, so the procedures are very complex.